With the advancement of the semiconductor integrated circuit fabrication technology for metal oxide semiconductor transistors, high dielectric constant (“high-k”) oxide materials are replacing SiO2 in many applications. However, unlike SiO2, high-k oxides are deposited rather than grown by thermal oxidation. With conventional high-k oxide deposition methods such as atomic layer deposition (“ALD”), when a high-k oxide material is deposited on a semiconductor substrate surface, the surface of the semiconductor substrate oxidizes as a result of the oxidizing pulses of the ALD process (O3 or H2O). This results in an undesired low-k oxide interfacial layer between the semiconductor substrate and the deposited high-k oxide layer. This low-k interfacial layer limits equivalent oxide thickness (“EOT”) scaling, increases interface trap density (Dit) for non-Si substrates such as those made from Ge or III/V semiconductors, and can potentially create integration problems, especially for non-Silicon surfaces.